Challenges Associated with Logic Optimization Tasks

Business challenges to overcome

Logic Optimization provides enormous value in keeping up with design project schedule.  Even though the layout is not yet committed to mask making, each RTL code change introduces a large amount of downstream re-design and re-verification efforts from synthesis, DFT to P&R. To mitigate the project delay, an efficient ECO methodology is often required.

Technical challenges to overcome

Even though logic optimization can help avoid re-starting the project from scratch, the changes made in RTL code impact the timing delay, static timing, formal verification and DFT, etc.  The key to success is the minimum change in terms of gate count and timing, and with the shortest turnaround time.

Benefits of Easy-Logic solution

Minimizing project delay by short turnaround time

Patented algorithm streamlines multiple aspects of the ECO process in a signle flow, from revised RTL code to scan chain fixing and preservation of special design requirements.  With a focus on total turnaround time, the algorithm delivers accurate results while optimizing efficiency.  Users can set breakpoints to verify the results in each step, or perform the entire ECO flow in a single run, saving users days to weeks of manual iteration.

Reducing the need of user's design expertise

EasylogicECO's patented algorithm eliminates the need for users to painstakingly trace the gate-level netlist in an attempt to identify ECO points.  Its highly automated flow requires minimal design knowledge from the user and ensures efficient, accurate results without the need for extensive manual intervention. 

Producing the most desirable ECO results

Automated iteration process for identifying optimal ECO points, minimizing patch logic, and optimizing path timing, significantly increases the success rate of functional ECO tasks.

Automatic ECO design flow

The ECO flow starts with a functional comparison between the revised RTL code and the original RTL. It is recommended to use the full system module as the input circuit, as it eliminates the need for designers to partition the design and provides a precise understanding of the ECO points. The tool then identifies the ECO points in the original netlist based on the required function change, and creates the logic patch based on the functions of the technology library, leveraging its capabilities to achieve optimal results. The tool seamlessly integrates the logic patch with the unchanged portion of the netlist, ensuring a optimized integration.  Its template-based batch mode execution guides the user through the ECO execution control process.

Design-For-Test (DFT) Features

This feature restores the DFT functionality in the ECO, specifically focusing on the scan chain portion.  It seamlessly adds/deletes DFFs for newly added/removed registers and creates the required scan chains for the functionally revised circuit while preserving the unchanged scan chains.  The revised scan chain is then stitched to the unchanged portion, creating updated scan chains. Additionally, it offers scan chain balancing and user-defined constraints, empowering users to manipulate the scan chain design to align with their specific design rules. It also ensures that specific test features, such as MBIST cells, are kept intact throughout the ECO process.

ECOs with large extent of impact

The tool automates the search for repetitive changes, feed-through changes, and other modifications throughout the entire design. It performs boundary optimization across hierarchies, allowing for efficient and effective handling of multiple functional ECO changes in a single run.

Special design requirements

In an ECO process, design requirements already exist in the original design must be honored, which may include ECO across power domains, ECO across clock domains, handling clock-gating and power isolation cells in low-power designs, as well as considering technology libraries for advanced process nodes such as 7nm or 5nm.

Formal verification support

The ECO tool generates references for downstream formal verification, enabling users to convert them into tool constraints for their preferred verification tool. These references contain information related to ECO netlist mapping and optimization.