The Challenges Associated with Patch Logic Creation Tasks

Business challenges to overcome

The business challenges related to logic-level functional ECOs, spanning from RTL code changes to creating optimal patch logic, include the following: 

     1. Time-to-market pressure 

     2. Design and verification overhead 

     3. Cross-team coordination 

     4. Potentially impact on downstream ecosystem

Technical challenges to overcome

The technical challenges of a logic-level functional ECO stem from the need to balance accuracy, efficiency, and integration within the design process. The challenges include: 

     1. Implementing gate-level modifications based on RTL changes 

     2. Identifying the best ECO points through netlist tracing 

     3. Achieving the smallest patch size 

     4. Ensuring short tool turnaround times  

     5. Achieving seamless design flow integration 

The key to success lies in making the minimum changes in terms of gate count and timing while achieving the shortest turnaround time.

Benefits of the Easylogic solution

Minimizing project delay by short turnaround time

The patented algorithm streamlines multiple aspects of the ECO process into a single flow, from analyzing revised RTL code to generating both the patch logic and the constraint files for subsequent design steps, such as functional verification or detailed routing. With a focus on total turnaround time, the algorithm delivers accurate results while optimizing flow efficiency.

The guided execution script templates help users eliminate pilot errors during critical design crunch periods. Users can set breakpoints to verify results at each step or execute the entire ECO flow in a single integrated run, saving days to weeks of manual iteration work.

Reducing the need of user's design expertise

EasylogicECO's patented algorithm eliminates the need for users to painstakingly trace the gate-level netlist in an attempt to identify ECO points, even when RTL signals have been optimized out, the netlist has been flattened, the change is instantiated multiple times, or the modified function spans across different design hierarchies.  

Its highly automated flow requires minimal design knowledge from the user and ensures efficient, accurate results without the need for extensive manual intervention. 

Producing the most desirable ECO results

The unique ECO algorithm generates the smallest possible patch logic and path delay, significantly increasing the success rate of the downstream ECO tasks.

Its automatic iterative process evaluates various combinations of suitable ECO points and their corresponding patch logic.  Additional logic optimization options and effort levels allow users to customize the patch logic for specific design needs, providing significant ECO flexibility to meet design constraints, flow integration requirements, and the task urgency.

RTL-based ECO design flow

The ECO flow begins with a functional comparison between the revised RTL code and the original RTL, ensuring that the differences accurately capture the genuine intent of the user's functional change.  EasylogicECO does not use netlist-to-netlist comparison to capture functional changes, as it typically results in false ECO requirements.

It is recommended to use the full system module as the input circuit, as it eliminates the need for designers to partition the design into smaller blocks and provides a precise understanding of the ECO points.

The tool generates the logic patch, along with the integration instructions for the original netlist and the contraints file for the subsequent netlist-to-RTL equivalence checking. 

Automatic netlist tracing for the best ECO points

The patented algorithm automates and simplifies the process of accurately locating the corresponding RTL design function in the netlist, even if the netlist has undergone the following changes:

     1. Extensive optimization during synthesis

     2. Flattening of hierarchies

     3. Signal names removed

     4. Replication and Instantiation

     5. Cross-hierarchy logic traversals

     6. Insertion of additional logic

     7. Timing and placement dependencies

Generating the smallest possible patch logic

Generating the smallest possible patch logic involves several key steps: 

     1. Accurately capture the ECO intent,

     2. Identifying suitable ECO points in the original netlist,

     3. Analyzing the corresponding patch function for each ECO point, 

     4. Optimizing the patch logic and path delay intensively.

In many cases, the best ECO change is not at the netlist location where the designer expects it to be.

ECO changes with large extent of impact

The tool automates the search for repetitive changes, feed-through changes, and other modifications throughout the entire design. It performs boundary optimization across hierarchies, allowing for efficient and effective handling of multiple functional changes in a single run.

Special design requirements

In an ECO task, the design requirements from the original design must be honored.  These may include handling ECO across clock or power domains (managing clock-gating and power isolation cells) and accouting for specific design rules in advanced process nodes such as 7nm or 5nm.

Formal verification support

The ECO process generates references for downstream formal verification, allowing users to convert them into constraints for their preferred verification tool. These references include details about ECO netlist mapping and optimization.

Applicable to ECO requirements at all stages of ASIC design

The solution is applicable throughout the entire ASIC design cycle, from the synthesis stage and DFT stage to the low-power design stage, P&R stage, final layout stage, and even the post-mask stage, if needed. Tool execution templates provided in the tool package support all design stages, ensuring seamless applicability.

Effortless plug-and-play integration with the design flow

The tool's easy integration, utilizing standard interface formats, enables users to incorporate it into their existing tool chains quickly and efficiently.