The Challenges Associated with Scan Chain Changes:

Business challenges to overcome

Test coverage is a critical requirement in many application segments.  When a functional ECO task adds, or removes, registers in the design, the associated scan chains and test patterns will have to be updated in order to maintain the required test coverage.

Technical challenges to overcome

During the ASIC design process, scan chain logic is automatically generated by DFT tools. However, designers in an ECO task team often need to manually correlate changes between the functional patch logic and the original scan chain netlist. Additionally, they must ensure compliance with all DFT rules in the scan chain modifications to preserve DFT coverage and testing efficiency.

Benefits of the Easylogic solution

Offering automatic scan chain fixing for designs of all sizes and complexities

Automatically updates the associated scan chains for the ECO netlist and ensures that various DFT constraints are met, greatly accelerating the ECO turnaround.  

Advanced physical-aware logic optimization algorithm delivers the smallest path delay by leveraging the physical information provided for the existing netlist and spare cells. 

A Plug-and-Play tool easily integrated with 3rd-party design flow

Incorporate flow interface features to allow designers using a third-party functional ECO solution to leverage its powerful scan chain fixing capabilities.  The interface utilizes standard data formats and TCL commands, reducing the integration barrier in the flow.

Ease of use and optimized patch for optimal scan chain results

EasylogicECO's flow requires minimal design knowledge from the users.  Its template-based batch mode execution guides the user through the scan chain fixing process and ensures efficient, accurate results without the need for extensive manual intervention. 

SDFF selection and conversion 

Converts regular DFFs in the logic patch into appropriate SDFFs that need to be inserted into the scan chain.

Scan chain stitching, removal and balancing 

Stitches SDFFs into the original scan chain while disconnecting unnecessary SDFFs.  Customizes the chain length based on user’s DFT constraints to meet the requirements of the test plan, enabling increased test coverage without compromising testing costs.

Support for advanced design requirements 

Ensures compliance with design rules while implementing scan chain revisions.  Identifies multi-clock domains, multi-power domains, and hold time violations and applies necessary adjustments, such as isolation/level shifter cells or lockup latches.

Physical-aware metal-only ECO algorithm

Utilizes physical information provided in the LEF/DEF format to enhance timing of the scan chain.

Resource options for a post-layout ECO task include spare cells, gate arrays, and filler cells.  When combined with physical information, optimizes the delay of scan chains by considering cell function and estimated wire delay.

Versatile design flow support

Supports various ECO flows for introducing changes of FFs, including EasylogicECO flow, 3rd-party ECO flow, and manual ECO flow. It utilizes standard formats for input/output data, enabling seamless integration with mainstream ASIC design flow.

Command line script operations

Script-based operation is simple, easy to learn and debug.  It only requires modifying specific script fields when migrating to other projects.