A functional ECO tool modifies the logic function of the chip in a later stage of the design process, usually after layout and routing, or even after masking.  Logic function of the APR netlist needs to be modified.

Application scenarios include improving chip performance, adding new features, or fixing design errors, whenever it is necessary to change the logic function of the chip design.

Functional ECO can be used at any design stage, even after tape-out.  But the ECOs differ in how the changes are implemented.  There is usually no strict limitation on available resources when ECO is carried out before tape-out.  However, for the ECO after tape-out, only those spare cells reserved for ECO can be used as the layout has been fixed.  In addition, since the number of spare cells is limited, there is also a resource limit on the scale of functional change.

Changing logic functionality by adding a netlist patch to the existing netlist can save a lot of project time.  Resynthesizing the netlist from the revised RTL to add new logic functions, subsequently going through the entire ASIC design flow all over again, is time consuming.

Yes.  Test circuit such as scan chains and MBIST will not be affected during the ECO process. Based on the needs of the new netlist, EasyECO generates SDFF(s) and also adds the SDFF(s) to the scan chain.

To learn more, please refer to the AppNote "Performing Scan Chain Fixing during Functional ECO Process" under the Resources section of our website.

Yes, EasyECO results are optimized for shortest paths.  Instead of calculating the delay of each cell unit, EasyECO selects appropriate patch logic based on logic level, the most appropriate spare units based on their physical locations, and clock signals from the clock tree for each generated test register based on the required scan chain function.

To learn more, please refer to the white paper "RTL-Based Full-Module Functional ECO Methodology" under the Resources section of our website.

Yes, EasyECO utilizes a unique reverse engineering analysis technology to identify signals that were removed during RTL synthesis, or scattered boundary signals, from the gate-level netlist. This enables the selection of the best ECO Point, ensuring successful completion of the ECO task.

EasyECO utilizes standard cells, spare cells (including filler cells and gate array), and replaced standard cells to construct patch circuit, and optimizes the patch for better timing results based on the physical information of the spare cells provided by the user.

EasyECO helps the design team complete ECO tasks in the shortest turnaround time, avoiding delays in the design cycle.  EasyECO uses a breakthrough RTL-based Functional ECO algorithm to effectively perform automatic, minimal logic function changes on the netlist to ensure that the changed netlist is consistent with the revised RTL function.

To learn more, please refer to the white paper "RTL-Based Full-Module Functional ECO Methodology" under the Resources section of our website.

Input files:

   1) RTL design

   2) Gate-level netlist (Verilog)

   3) Standard cell library (Liberty)

Required input files according to specific the design requirements:

   1) SVF or VSDC file

   2) Physical design files (DEF, LEF)

EasyECO output files:

   1) A netlist that satisfies the ECO function

   2) Third-party tool scripts that perform the ECO function downstream

EasyECO automatically modifies the corresponding gate-level netlist according to designer’s functional changes of the RTL code, so the modified gate-level netlist has the same function as the modified RTL code.  EasyECO changes the connections of standard cells of the gate-level netlist, adding new cells or deleting old cells, and finds the minimum scale of logic change.

To learn more, please refer to the white paper "RTL-Based Full-Module Functional ECO Methodology" under the Resources section of our website.

EasyECO offers significant advantages over traditional ECO solutions, including a highly efficient algorithm that improves the utilization of spare resources and speeds up total operations. 

Notably, EasyECO enables a significantly larger scale of functional ECO, providing a new level of capability to the ASIC design community. Test results indicate that EasyECO requires on average 30% fewer instance resources compared to traditional solutions, with some cases achieving a reduction of 10 times or more. Tool run time is also over 10 times faster, with speed improvement increasing as the design scale grows larger.

EasyECO considers the characteristics, and design requirements, of advanced processes 10nm and below and performs additional logic and physical optimizations.

The contact information for each region is shown under the [Contact] web tab.

1) 64-bit Linux workstation, kernel version not lower than 2.6 (Centos 6/7, ArchLinux, RedHat, SUSE, Ubuntu)

2) At least 64GB RAM memory

3) At least 100GB free disk space

4) Multi-core CPU processor

Our team of Applications Engineers are readily available to assist you with any technical queries through multiple channels including email, SMS, social media platforms, and VoIP.  In addition to this, our technical support services include providing comprehensive online training and guidance for software installation. To initiate a technical discussion with us, please send us an email at info@easylogic.hk.

Please check out the training schedule on the [Events] webpage and register.  Events webpage is under [Company] web tab.

Training courses are delivered either in-person or online.

We welcome you to discuss any design-related issues you may have with our team of Easy-Logic FAEs. 

You may send us an email request at info@easylogic.hk, or alternatively, use the Contact Us form available under the [Contact] web tab to describe your questions.  Our FAEs are available to assist you through various communication channels such as email, instant messaging, or video conferencing. We look forward to hearing from you.